OIC

OIC

Network On-Chip Bus Interconnect IP

OIC

TM

Get to know the ORBIT Memory Subsystem IP that consists of an interconnect, memory controller, and PHY IPs that work in unison to create maximum system synergies. 

Experience the ORBIT DDR Memory Controller's exceptional performance, high utilization, and low latency. 

Meet high-speed memory PHY IPs that deliver the lowest power and area, enabling solutions across AI/ML, high-performance computing (HPC), and mobile and automotive.

OIC

TM

The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow. It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.

Key Features

Memory Subsystem IP

  • Tuning the performance for the entire SoC memory subsystem

  • ActiveQoS bandwidth and latency control for the entire SoC memory subsystem

High-Speed HyperPath Technology

  • More than 1GHz at 28nm processor or more than 800MHz at low power 28nm

Flexible Floorplan & Physical Design Friendly

  • Long-distance Asynchronous Bridge (LDA) technology solves long and narrow topology design

Ultra Low Power

  • Enables <200uW idle power for entire backbone (+3M gate size)

Area (Wire Congestion)

  • Less than 50% of typical AXI-based backbone bus area

Design Tools

  • End-to-end RTL and verification package generation with ORBIT toolkit

Key Advantages

High Performance

  • Proprietary HyperPath technology enabling 2x performance

  • Extremely low latency with LDA technology

  • Dynamic priority control in OIC and OMC, based on observed latency & bandwidth (ActiveQoS)

Low Power Consumption

  • Advanced Clocking enables extremely low power

  • Proactively clock-gating

High Flexibility

  • Automated end-to-end RTL generation with an ORBIT design toolkit

  • Fast & easy SoC design of high-speed and long-distance interconnect

Safety & Security

  • End-to-end ECC (SECDED) support​

  • End-to-end at-speed BIST

 
 

Long-distance Asynchronous (LDA   ) Bridge

TM

  • OPENEDGES' proprietary protocol, LDA, connects data transmission physically far apart domains without register slices.

  • Provides significantly smaller gate count, and uncomplicated physical design than the register slice scheme

  • High-speed data transfer with source-synchronous clocking scheme

    • Well-known technology in the high-speed interface (including DDR interface)​

    • Eliminate clock-tree expending for the long and narrow backbone interconnect

    • Optimal LDA retimer controls inter-signal skews for very long wire

LDA Bridge Diagram.png
 

ORBIT    Network On-Chip HyperPath

TM

TM

  • A proprietary protocol, HXI, is highly optimized for on-chip interconnect with reducing wires

  • Path based clock control using HXI side-band channel

  • Enable 2x performance using HyperPath Express interface

  • Rich featured and high-performance switching components

  • With ORBIT Toolkit, predetermined and preoptimized routing path provides better performance and low power consumption

 
 

OIC Deliverables

OIC is packaged with the following items to all eligible companies: 

  • IP Core RTL

  • Simulation Environment

  • Synthesis, Lint Script

  • Detail Documentation