High performance and area-saving Network On-Chip (NoC),
OPENEDGES
On-Chip Interconnect, OIC
OPENEDGES On-Chip Interconnect IP, OIC
OPENEDGES On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow. It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.
Key Features
Memory Subsystem IP
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Tuning the performance for the entire SoC memory subsystem
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ActiveQoS bandwidth and latency control for the entire SoC memory subsystem
High-Speed HyperPath Technology
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More than 1GHz at 28nm processor or more than 800MHz at low power 28nm
Flexible Floorplan & Physical Design Friendly
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Long-distance Asynchronous Bridge (LDA) technology solves long and narrow topology design
Ultra Low Power
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Enables <200uW idle power for entire backbone (+3M gate size)
Area (Wire Congestion)
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Less than 50% of typical AXI-based backbone bus area
Design Tools
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End-to-end RTL and verification package generation with OPENEDGES toolkit
Key Advantages
High Performance
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Proprietary HyperPath technology enabling 2x performance
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Extremely low latency with LDA technology
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Dynamic priority control in OIC and OMC, based on observed latency & bandwidth (ActiveQoS)
Low Power Consumption
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Advanced Clocking enables extremely low power
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Proactively clock-gating
High Flexibility
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Automated end-to-end RTL generation with an OPENEDGES design toolkit
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Fast & easy SoC design of high-speed and long-distance interconnect
Safety & Security
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End-to-end ECC (SECDED) support
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End-to-end at-speed BIST
OIC Deliverables
OIC is packaged with the following items to all eligible companies:
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IP Core RTL
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Simulation Environment
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Synthesis, Lint Script
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Detail Documentation
Long-distance Asynchronous (LDA™) Bridge
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OPENEDGES' proprietary protocol, LDA, connects data transmission physically far apart domains without register slices.
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Provides a significantly smaller gate count and uncomplicated physical design than the register slice scheme
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High-speed data transfer with a source-synchronous clocking scheme
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Well-known technology in the high-speed interface (including DDR interface)
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Eliminate clock-tree expending for the long and narrow backbone interconnect
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Optimal LDA retimer controls inter-signal skews for very long wire
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OPENEDGES Network On-Chip HyperPath™
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A proprietary protocol, HXI, is highly optimized for on-chip interconnect with reduced wires
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Path-based clock control using HXI side-band channel
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Enable 2x performance using HyperPath Express interface
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Rich featured and high-performance switching components
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With OPENEDGES Toolkit, predetermined and preoptimized routing path provides better performance and low power consumption