High performance and area-saving Network On-Chip (NoC),
OPENEDGES
On-Chip Interconnect, OIC
OPENEDGES On-Chip Interconnect IP, OIC
OPENEDGES On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow. It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.
Key Features
Memory Subsystem IP
-
Tuning the performance for the entire SoC memory subsystem
-
ActiveQoS bandwidth and latency control for the entire SoC memory subsystem
High-Speed Technology
-
More than 1.5GHz at 5nm processor
Flexible Floorplan & Physical Design Friendly
-
Long-distance Asynchronous Bridge (LDA) technology solves long and narrow topology design
Ultra Low Power
-
Enables <200uW idle power for entire backbone (+3M gate size)
Area (Wire Congestion)
-
Less than 50% of typical AXI-based backbone bus area
Design Tools
-
End-to-end RTL and verification package generation with OPENEDGES toolkit
-
Intuitive NoC Topology Design & Configuration GUI Toolkit
Key Advantages
High Performance
-
Proprietary HyperPath technology enabling 2x performance
-
Extremely low latency with LDA technology
-
Dynamic priority control in OIC and OMC, based on observed latency & bandwidth (ActiveQoS)
Low Power Consumption
-
Advanced Clocking enables extremely low power
-
Proactively clock-gating
High Flexibility
-
Automated end-to-end RTL generation with an OPENEDGES design toolkit
-
Fast & easy SoC design of high-speed and long-distance interconnect
Safety & Security
-
End-to-end ECC (SECDED) support
-
End-to-end at-speed BIST
OIC Deliverables
OIC is packaged with the following items to all eligible companies:
-
IP Core RTL
-
Simulation Environment
-
Synthesis, Lint Script
-
Detail Documentation
Long-distance Asynchronous (LDA™) Bridge
-
OPENEDGES' proprietary protocol, LDA, connects data transmission physically far apart domains without register slices.
-
Provides a significantly smaller gate count and uncomplicated physical design than the register slice scheme
-
High-speed data transfer with a source-synchronous clocking scheme
-
Well-known technology in the high-speed interface (including DDR interface)
-
Eliminate clock-tree expending for the long and narrow backbone interconnect
-
Optimal LDA retimer controls inter-signal skews for very long wire
-
