top of page

OPENEDGES to Demonstrate Latest NPU IP, ENLIGHT at CVPR 2022

Seoul, South Korea, June 21st, 2022 --- OPENEDGES Technology, Inc. (hereinafter referred to as OPENEDGES), the world’s leading memory system and AI platform IP provider, announced today that it will exhibit its mixed-precision NPU & DDR IP solution at the IEEE/CVF Computer Vision and Pattern Recognition (CVPR) conference expo, June 21-23 at the Ernest N. Moral Convention Center in New Orleans, Louisiana.

OPENEDGES is presenting its industry-first 4-/8-bit mixed-precision computation NPU IP, ENLIGHT. This sophisticated IP is market-proven and designed for processing neural network inference in an edge environment. It provides highly accurate neural network prediction results while offering unrivaled efficiencies in power consumption, area, and DRAM bandwidth. Unlike most existing NPU IPs in edge applications, ENLIGHT is capable of switching between 4-bit and 8-bit precision mode on-the-fly according to the quantization results from the quantization toolkit. ENLIGHT’s optimized network model is based on a software stack that features an optimizer, compiler, and quantization toolkit. Moreover, it supports multi-core scalability to achieve higher TOPS (Tera Operations).

IMAGE 1: OPENEDGES’ NPU IP, ENLIGHT Hardware Architecture Diagram

OPENEDGES is showcasing real-time demos of its ENLIGHT IP using the FPGA boards with comparisons of 4-/8-bit quantized network variations, as well as its ORBIT memory system — consisting of NoC (Network On-Chip), DDR controller (for DDR3/4, LPDDR3/4/4x/5/5x), and DDR PHY (LPDDR4/4x/5/5x, GDDR6) IPs — and how they are tightly coupled with the NPU IP to achieve maximum synergy in efficiency and DRAM bandwidth. On-site, OPENEDGES is recruiting prospective employees for its various offices worldwide.

“The core of the OPENEDGES’ philosophy is connecting people and the technology through OPENEDGES’ IP technology,” said Sean Lee, the CEO of OPENEDGES Technology, Inc. “As the only vendor that offers a fully integrated memory system and NPU IP, we are thrilled to demonstrate how our IPs can be combined to create optimal synergy and assist our customers in designing their System-on-Chips (SoCs).”


bottom of page