The innovative architecture driving the highest utilization and lowest latency
OPENEDGES
DDR Memory Controller, OMC
OPENEDGES Memory Controller, OMC
Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduling algorithm and high-speed implementation. Designed to address the needs of next-generation SoCs, OMC saves a significant amount of area and power while supporting the highest levels of the DRAM bandwidth.
OMC integrates seamlessly with the OPENEDGES DDR PHY(OPHY) and On-Chip Interconnect (OIC) to deliver a complete memory subsystem. OMC also supports third-party DDR PHYs, providing full functional verification for use with any PHY implementation.
Key Features
DRAM Support
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JEDEC compliant LPDDR6/5x/5/4x/4/3, DDR4/3, GDDR6, HBM
High Performance
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A proprietary out-of-order scheduling algorithm
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Dual-PHY control for 2x DRAM channel bandwidth with a single OMC instance
Low Power Consumption
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Ultra-low power consumption with HW-controlled dynamic DRAM frequency scaling
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Automatically handles training activities required for frequency change
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Automated DRAM power management
Special Features
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BFE (Bus Front End) for multi-master ports (optional)
Workload-Driven Performance Optimization
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Intuitive visualization and analysis of memory subsystem architecture and performance
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Workload-driven memory subsystem architecture and QoS optimization
Key Advantages
Intensive DRAM Utilization
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Over 90% DRAM utilization using a proprietary out-of-order scheduling algorithm
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Optimal pipeline architecture
Ultra-Low Power Consumption
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Hardware-controlled dynamic DRAM frequency scaling
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Automates training activities required for frequent changes
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Highly area-efficient
Extremely Low Latency
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Low latency even in high utilization scenarios
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Suppression of peak latency using the latency-aware algorithms
Safety & Security
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Inline ECC AN link ECC
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Features link error detection, security firewall
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Retry on data link error
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Achieved ISO 26262
DDR Memory Type
OMC Configurable Options
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DRAM types (LPDDR6/5x/5/4x/4, DDR5/4x/4/3, GDDR6, HBM3)
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Channel DQ width (x4, x8, x16, x32, x64)
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Number of AXI master ports (up to 5)
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AXI master data width and frequency
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Customizable Request queue depth
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Configurable write and read data queue depth
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Active QoS with OPENEDGES On-chip Interconnect IP
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AES-Based integrated memory encryptor
OMC Deliverables
OMC is packaged with the following items to all eligible companies:
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IP Core RTL
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Standalone Simulation Environment
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Management SW
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IP Documentation