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Verification Group Lead - San Jose/Austin

OPENEDGES develops AI Edge Computing semiconductor IPs,

so that more people can enjoy AI technology closer.

📍 Location: San Jose, CA, USA or Austin, TX, USA

📍 Position: Verification Group Lead

OPENEDGES is world's the only total memory system and AI platform IP solution company that has delivered NPU, memory controllers, DDR PHY, and on-chip interconnect IPs all together in one place since 2017.

Roles & Responsibilities:

OPENEDGES is building a team in the US to develop a configurable cache-coherent NoC to add to its portfolio enabling AI SoCs. It is a significant opportunity to work on a design from scratch that will enable high performance, highly efficient AI designs requiring cache coherency. This role can be in San Jose, CA or Austin, TX with Hybrid/Remote work a possibility.

As Verification Group Lead you will design and implement the infrastructure and methodologies for verifying a better cache-coherent NoC interconnect IP. You will help build the team, develop the verification IP required, and drive execution of your verification plan.

  • Verification of the next-generation Cache Coherent NoC Interconnect

  • Establish design verification methodology for the very large design space of flexible and scalable NoCs

  • Create verification infrastructure and design flow by collaborating with the software group

  • Collaborate with the architect and design engineers for functional and performance verification of the interconnect, cache coherency and memory consistency

  • Participate in recruiting new engineers into the team and mentor/develop existing team members

Job Requirements:

  • Bachelor’s of Master’s degree in Computer Science or Electrical/Computer Engineering

  • 10+ years of work experience in designing, verifying, and validating complex hardware systems

  • Proven experience in pre-silicon verification/RTL Design

  • Experience architecting one or more verification environments, developing the verification strategies and methodologies, and designing verification IP that enabled high quality, efficient, and comprehensive verification of complex designs.

  • Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols

  • Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches

  • Shown software engineering skills including understanding of object-oriented programming, data structures and algorithms

  • Experience with functional coverage verification methods


  • The ability to work in an entrepreneurial environment that fosters a collaborative/team atmosphere

  • Experience with startup environments or venture backed firms

  • A self-starting orientation with the intense desire/drive to “make things happen.”


  • Medical Plan

  • Dental & Vision Benefits

  • Life & Accidental Death & Dismemberment (AD&D) Insurance

  • 401K


  • 2540 N.First Street, Suite 101, San Jose, CA, US (On-site/Hybrid/Remote)

  • Austin, TX (office coming soon)

How to Submit Your Resume:

  • Click Apply to submit your application online


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