The Memory System

The ORBIT Memory System, designed for high performance System-on-Chips, consists of interconnect, memory controller, and PHY IPs that work in unison to create maximum synergies.

The ORBIT Memory System provides ActiveQoS advanced traffic control. As part of ActiveQoS, both OIC and OMC prioritize traffic based on its urgency and master's property to deliver latency-sensitive traffic on time. ActiveQoS uses the buffer status from the OMC and slave monitor IPs to manage traffic from the masters. By interacting with the memory controller, ActiveQoS reduces latency and bandwidth in OIC. As a result, ActiveQoS allows OIC to maintain steady traffic while avoiding blocking and congestion caused by overcrowding.

• Automated adaptation of QoS knobs based on real latency observed in silicon

• Enabled by a combination of NoC and memory controller

• Perfect solution to Head-of-Line (HOL) blocking issue with maintaining utilization