OPENEDGES
TOTAL MEMORY SYSTEM
Discover a deep learning accelerator that accelerates inferencing computation with excellent efficiency and unmatched compute density.
Get to know OPENEGES Memory Subsystem IP that consists of an interconnect, memory controller, and PHY IPs that work in unison to create maximum system synergies.
The Beauty of State-of-Art
OPENEDGE Total Memory Subsystem
The memory subsystem of the new generation of AI chips needs to have numerous features, such as the ability to reduce latency, consume less energy, provide higher bandwidth, support more DRAM protocols, and reserve channels for newer DRAM technologies, thereby extending product cycles, increasing application coverage, and improving product market competitiveness. OPENEDGES Memory Subsystem has been rapidly designed and engineered to incorporate it into SoCs for various AI markets.
Learn about OPENEDGES Memory Subsystem that comprises an NoC bus interconnect (OIC), a DDR memory controller (OMC), and a DDR PHY (OPHY) working in unison to deliver the ultimate synergies.
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ActiveQoS Within
OPENEDGES Memory Subsystem
TM
OPENEDGES Memory Subsystem provides ActiveQoS advanced traffic control. As part of ActiveQoS, OIC, and OMC prioritize traffic based on urgency and the manager's property to deliver latency-sensitive traffic on time. ActiveQoS uses the buffer status from the OMC and subordinate monitor IPs to manage traffic from the manager. ActiveQoS reduces latency and bandwidth in OIC by interacting with the memory controller. As a result, ActiveQoS allows OIC to maintain steady traffic while avoiding blocking and congestion caused by overcrowding.
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Automated adaptation of QoS knobs based on real latency observed in silicon
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Enabled by a combination of NoC and memory controller
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A perfect solution to Head-of-Line (HOL) blocking issue with maintaining utilization
