Get to know the ORBIT Memory Subsystem IP that consists of an interconnect, memory controller, and PHY IPs that work in unison to create maximum system synergies.
Experience the ORBIT DDR Memory Controller's exceptional performance, high utilization, and low latency.
OPHY DDR PHY
Features a state-of-the-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performance and low-power environments. This architecture enables OPHYs to overcome issues with long-term impedance drift and clock phase drift, enabling impedance and clock phase updates without interruption of data traffic. Programmable timing at the OPHY boundary combines flexibility with analog precision, resulting in low read/write latency between the ORBIT Memory Controller (OMC) and the DRAM.
OPHYs are designed with subsystem and system-level considerations in mind. Built-in power management logic and advanced PLL design allow aggressive power state management and optimal system power usage. Tight integration with the ORBIT Memory System enables ActiveQoS bandwidth and latency control for maximum performance of the SoC memory subsystem. At the system level, OPHYs have been designed to minimize package substrate layer and PCB layer requirements, enabling usage in cost-sensitive applications.
The Six Semiconductor
The Six Semiconductor (TSS) is a Canadian technology company focused on developing high-speed memory PHY IP solutions, and is a wholly-owned subsidiary of OPENEDGES. The TSS team has a mission to develop high-speed memory PHY IP with the lowest power and area, providing solutions that range from AI/ML, high-performance computing (HPC), to mobile and automotive applications in multiple standards, technologies, and foundries. From digital to analog, the team understands every part of the system and uses the best of full custom and RTL digital logic to create a cohesive system.
Visit www.thesixsemi.com to learn more about TSS.
Compliant with PHY standards
- JEDEC compliant LPDDR5x/5/4x/4, GDDR6, HBM3 support
DFI Interface Compliant
- LPDDR54: 8-/16-/32-bit data width per channel
- GDDR6: 16-bit data width per channel; pseudo-channel mode
- Supports multiple DFICLK: CK: WCK ratio
- Multiple DFICLK: CK: WCK ratios
- Up to 4 ranks with Tx and Rx channel equalization
Maximum Data Rates
- Up to 8533 Mbps data rate for LPDDR5x
- Up to 16 Gbps data rate for GDDR6
Programmable State Machine (PSM)
- Proprietary microcontroller and custom ISA enable customizable DFT features and multiple LPDDR standard support efficiently while reducing the area
Multiple FSPs and the LP States
Supports up to 4 frequency set points (FSPs)
Supports multiple low power states for system power optimization
DDR PHY Availability
Configurability with Flexible Applications
Configurable channel and floor-plan allow connection to different DRAM package types and lane ordering
Minimal package substrate/PCB layer requirements enables PHY usage in low-cost applications
PSM enables accelerated firmware-based training
Ultra-fast fractional training
Programmable PHY boundary timing provides low read/write latency
Fast switching between FSPs
Channel equalization and fast timing adjustment circuits enable 4 rank support to maximize capacity
Power-saving modes with a variety of exit times
Multiple voltage domains to optimize voltage versus frequency
Hard & Soft IP
GDSII, LEF, LVS, timing models, etc
Verilog behavior models and encrypted RTL
Synthesis and STA constraints
Example test benches
PHY Technical Reference Manual
Implementation, Package, and PCB design guidelines