📍 Location: San Jose, CA or Austin, TX, USA
📍 Position: Design Verification Engineer (Full-time)
Job Summary:
OPENEDGES Square Corporation (OSC) is seeking highly motivated, qualified individuals to join the Design Verification (DV) team for our upcoming configurable cache coherent Network on a Chip (NoC) program. This exciting position based in San Jose Ca, or Austin Tx, offers opportunities to work within a veteran team of industry experts to solve state of the art DV challenges as they apply to the complexities of a Coherent Mesh Fabric. Currently we are staffing the team for several levels and are interested in folks who are attracted to working in entrepreneurial environments with small to mid-size teams. We are looking for team players with alignment for these types of products with aggressive schedules, have hands-on experience in all aspects of DV efforts, and can bring to bear their expertise in making our effort a success.
Roles & Responsibilities:
The successful Design Verification Engineer (DVE) at OSC will be responsible for:
Collaborating with architecture/design teams to understand the NoC design.
Apply state of the art methods to author comprehensive DV Plans/schedules/tracking.
Establish and/or contribute to required DV flows/methodologies.
Work with vendors to integrate UVM based Verification IP into a complete testbench solution.
Determine and implement required UVM based correctness checking.
Creating a UVM based constrained random stimulus suite to achieve high coverage.
Implement UVM based tracking methods to acquire and track coverage to closure.
Hands on debugging simulation fails down to root-cause (Verilog RTL).
Demonstrating good communication skills, works well on small dynamic teams.
Required Qualifications:
The ideal OSC DVE candidate will have a reasonable mix of the following credentials:
MSEE/MSCE+5 years, BSEE/BSCE+(5-10) years relevant experience/track record.
Knowledge/experience in the following areas:
Cache Coherent memory architectures and NoC designs.
AMBA buses: CHI, CSL, AXI(n), ACE, APB.
Standard IP: DDR(x), PCI, PCIe, ARM, X86, RISC-V.
Hands on development of testbenches using Verilog, SV/UVM, RAL, SVA, ABV, UPF, XProp.
Experience installing/configuring vendor IP for highly integrated testbench design.
Experience using industry standard toolsets.
Scripting languages: PERL/Python/Tcl/XML.
Preferred Qualifications:
Formal verification methods, emulation experience.
Benefits:
Medical, dental, and vision benefits
Life insurance
401k retirement plan
Paid time off, paid holidays, sick leave, etc.
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