📍 Location: San Jose, CA or Austin, TX, USA
📍 Position: Junior Design Verification Engineer (Full-time)
Job Summary:
OPENEDGES Square Corporation (OSC) is seeking highly motivated, qualified individuals to join the Design Verification (DV) team for our upcoming configurable cache coherent Network on a Chip (NoC) program. This exciting position based in San Jose Ca, or Austin Tx, offers opportunities to work within a veteran team of industry experts to solve state of the art DV challenges as they apply to the complexities of a Coherent Mesh Fabric. Currently we are staffing the team for several levels and are interested in folks who are attracted to working in entrepreneurial environments with small to mid-size teams. We are looking for team players with alignment for these types of products with aggressive schedules, have hands-on experience in all aspects of DV efforts, and can bring to bear their expertise in making our effort a success.
Roles & Responsibilities:
The successful Junior Design Verification Engineer (DVE) at OSC will be responsible for:
Productive member of DV teams and experience in various DV related activities.
Understands, and can explain basic DV concepts and related issues.
Eager and curious to explore new and challenging learning opportunities.
Has had some experience using standard DV tools and debug techniques.
Understands testbench architecture through System Verilog and UVM.
Good communication skills/collaborates well with team, mentors and leads.
Driving assigned tasks to completion with best practice methods.
Required Qualifications:
For this position, the ideal candidate will have a reasonable mix of the following credentials:
MSEE/MSCE, BSEE/BSCE+(2-7) years relevant employment history.
Academic background in computer architecture/OOP/algorithms/logic design.
Academic knowledge, some experience in one or more of the following areas:
Cache Coherent memory architectures and NoC designs.
AMBA buses: AXI(n), ACE, APB.
Standard IP: DDR(x), PCIe, ARM, X86, RISC-V.
Exposure to testbenches using Verilog, SV/UVM.
Experience using industry standard toolsets.
Experience in one or more Scripting languages: PERLPython/Tcl/XML.
Benefits:
Medical, dental, and vision benefits
Life insurance
401k retirement plan
Paid time off, paid holidays, sick leave, etc.
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