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The Six Semiconductor of OPENEDGES Collaborates with imec.IC-link US to Tape-out Two 7nm Testchip

Markham, Ontario, February 16th, 2023 --- The Six Semiconductor, Inc. (TSS), a subsidiary of OPENEDGES Technology, Inc and a leading supplier of cutting-edge high-speed memory PHYs in multiple standards, technologies, and foundries, announced today that it has successfully taped out two memory sub-system validation testchips at the same time in a 7nm process. Throughout the entire design process, TSS worked in collaboration with imec.IC-link US, a complete ASIC solutions provider and a part of imec, a world-leading R&D and innovation hub in nanoelectronics and digital technologies.

The first testchip taped out was TSS’s LPDDR5X/5/4X/4 PHY IP validation vehicle, supporting the JESD209-5B LPDDR5X DDR standard up to 8533Mbps. LPDDR5X is currently the fastest LPDDR DRAM standard, with a speed extension above the 6400Mbps data rate that LPDDR5 has to offer. The LPDDR5X PHY can operate with backward compatibility to LPDDR4 mode, providing flexibility to end-customers’ product DRAM selection requirements. Complete with OPENEDGES’ DDR controller (OMC™), which is equipped with advanced features in power management, and a generation 2 PHY architecture, the LPDDR5X PHY (OPHY™) aims to take the crown in PPA in the low-power DDR memory subsystem market.

The second validation vehicle taped out concurrently was the company’s HBM3 PHY testchip, designed to operate up to 8.4Gbps in a 2.5D integration platform. The HBM3 test platform is completed with the HBM3 OMC™, and HBM3 OPHY™ on the same test die, and the HBM3 die stack is integrated together in a 2.5D assembly. In the process of implementing this 2.5D system, Imec.IC-link worked with TSS on the evaluation, design, optimization, and all the logistics. As opposed to traditional DRAM, the HBM3 memory subsystem requires the entire SoC, silicon interposer, and package substrate to be designed concurrently, which requires meticulous planning and know-how at the full system level.

“imec.IC-link’s talented design team was a blessing to work with throughout these two parallel projects,” said Richard Fung, CEO of TSS. “With an extremely short design cycle and a fixed timeline, project management, and design execution were crucial to tape-outs of our two testchips on time. We look forward to working with imec.IC-link again soon on our next projects.”

“imec.IC-link US is proud to partner with TSS on the leading-edge high-speed memory PHY development and delivery of these two 7nm test chips.“ said Yiyi Wang, Head of imec.IC-link US. ”Delivering the GDSII from Netlist hand-off in only a few months was not trivial. And the effort spent on an advanced 2.5D integration manufacturing proven flows was significant. 2.5D SoC integration requires a highly complex co-design phase, including chip backend layout design, interposer design, substrate design, and BGA package design. We are glad to have our in-house capabilities proven through this turnkey ASIC project with TSS and look forward to supporting their needs in leading node technologies and advanced packaging again in the future.”

“Designing and coordinating the coherency of an HBM3 PHY, the testchip, along with the 2.5D integration platform is no small task. I’m very proud of our design team for executing this extremely challenging project in such a short amount of time.”, said Jason Mangattur, the VP of Silicon Operations at TSS.

"The successful tape-out of these two advanced memory subsystem validation testchips is a testament to the exceptional work of our team and our partnership with imec.IC-link US. They were instrumental in providing the technical know-how and support required to bring these cutting-edge technologies to fruition. Their expertise in ASIC solutions enabled us to achieve our goals in a timely manner and with the highest level of quality. We are grateful for their support and collaboration on these projects and look forward to working with them again in the future," said Sean Lee, CEO of OPENEDGES Technology.



OPENEDGES Technology, Inc. is a premier provider of memory subsystem IPs for the semiconductor industry. They offer a wide range of state-of-the-art solutions, including DDR memory controllers, DDR PHY, NoC interconnect, and NPU IPs that are widely adopted by customers worldwide. Their IPs comply with JEDEC standards, including LPDDR5x/5/4x/4/3, DDR5/4/3, GDDR6, and HBM3, ensuring their compatibility with the latest DDR technology trends. In 2019, they acquired The Six Semiconductor, Inc. (TSS), which specializes in high-speed memory PHYs across multiple technologies. As a publicly listed company on the Korean Stock Exchange Market (394280. KQ), OPENEDGES is well-positioned to continue its growth and maintain its leadership in the memory system IPs market.

Learn more about the company and its offerings by visiting the website at

About TSS

TSS is a Canadian technology company and a wholly owned subsidiary of OPENEDGES, which specializes in developing advanced high-speed DDR PHY IP solutions that cater to a wide range of applications such as AI/ML, high-performance computing (HPC), mobile devices, and automotive. The company's product portfolio includes PHY IPs for various memory standards, including LPDDR5x/5/4x/4, GDDR6, and HBM3, that are optimized for power and area. TSS's solutions are designed to be compatible with multiple technologies, foundries, and process nodes. The company's team of experts has a wealth of experience in the field and are dedicated to providing the industry with high-quality and reliable DDR PHY IP solutions. To learn more about TSS's products, visit their website at


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